1. Field of the Invention
The present invention relates to an operational amplifier with a rail-to-rail common-mode input and output range, and more particularly, to an operational amplifier with a rail-to-rail common-mode input and output range having a push-pull output stage, least current paths, a simplest circuit structure and a lowest operating voltage.
2. Description of the Prior Art
With the advance of semiconductor technologies, operating voltages of integrated circuits become lower and lower, such as for the 0.25 μm CMOS process, the typical operating voltage is as low as 2.5V. However, the threshold voltages needed to turn on the CMOS transistors (PMOS/NMOS) is about 0.6V, and thus, for the design of analog circuits, problems of insufficient input and output common-mode voltage of an operational amplifier often occur. In order to solve these problems, the operational amplifier needs to have a rail-to-rail common-mode input and output range.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art rail-to-rail operational amplifier 10. The operational amplifier 10 is a two-stage amplifier, and includes a differential input stage 11 and an output stage 12. The differential input stage 11 includes a first differential input pair 110 and a second differential input pair 120. The first differential input pair 110 comprises a pair of matched NMOS transistors M5 and M6 and a first current source 11. The first current source 11 is coupled to the source electrodes of the transistors M5 and M6, and is utilized for providing quiescent currents of the first differential input pair 110. The gate electrodes of the transistors M5 and M6 are respectively coupled to a negative input terminal VN and a positive input terminal VP, and are utilized for receiving signals being amplified. Additionally, the drain electrodes of the transistors M5 and M6 are coupled to nodes D and E, respectively. Similarly, the second differential input pair 120 comprises a pair of matched PMOS transistors M7 and M8 and a second current source 12. The second current source 12 is coupled to the source electrodes of the transistors M7 and M8, and is utilized for providing quiescent currents of the second differential input pair 120. The gate electrodes of the transistors M7 and M8 are respectively coupled to the positive input terminal VP and the negative input terminal VN. The drain electrodes are coupled to nodes C and B.
The output stage 12 is a summing circuit, driven by a first supply voltage VSUP1 and a second supply voltage VSUP2, for outputting a summation result of output signals of the first differential input pair 110 and the second differential input pair 120 through an output terminal VOUT, and includes a first current mirror 130, a second current mirror 140 and a third current mirror 150. The first current mirror 130 comprises PMOS transistors M1 and M2, and is utilized for mapping a current ID passing through the node D to the node C. Note that, the operations of the first current mirror 130 is well known by those skilled in the art, so as not to be narrated herein. In the same manner, the second current mirror 140 comprises PMOS transistors M3 and M4, and is utilized for mapping a current IE passing through the node E to a node A; and the third current mirror 150 comprises NMOS transistors M9 and M10, and is utilized for mapping a current IC flowing out of the node C to the node B. The output terminal VOUT is coupled to the nodes A and B, and is utilized for outputting the summation result of the output signals of the first differential input pair 110 and the second differential input pair 120.
Therefore, for the first differential input pair 110, when the common mode voltage of the input signal (VP+VN)/2 is in a low voltage range, such as lower than the second supply voltage VSUP2 plus a threshold voltage of the transistors M5 and M6, the transistors M5 and M6 cannot be turned on, so that the first differential input pair 110 cannot work normally. Thus, the effective working range of the first differential input pair 110 is restricted between the first supply voltage VSUP1 and the second supply voltage VSUP2 plus the threshold voltage of the transistors (VSUP2+VTH), that means, the common-mode voltage input range of the first differential pair 110 can be as high as the first supply voltage VSUP1. Conversely, for the second differential input pair 120, when the common mode voltage of the input signal (VP+VN)/2 is in a high voltage range, such as higher than the first supply voltage VSUP1 minus a threshold voltage of the transistors M7 and M8, the transistors M7 and M8 cannot be turned on, so that the second differential pair 120 cannot work normally. Thus, the effective working range of the second differential input pair 120 is restricted between the first supply voltage VSUP1 minus the threshold voltage of the transistors (VSUP1−VTH) and the second supply voltage VSUP2, that means, the common-mode voltage input range of the second differential pair 120 can be as low as the second supply voltage VSUP2.
Therefore, as shown in FIG. 1, the operational amplifier 10 has advantages such as less current paths and less transistors, and so on. However, since the operational amplifier 10 does not have a push-pull output stage, the applications of the operational amplifier 10 are greatly limited.
Please refer to FIG. 2. FIG. 2 is a schematic diagram of another prior art rail-to-rail operational amplifier 20. The operational amplifier 20 is disclosed in U.S. Pat. No. 5,311,145 “Combination Driver-Summing Circuit for Rail-to-Rail Differential Amplifier”. In the operational amplifier 20, a floating current source IS, coupled between the drain electrodes of transistors QS5 and QS7, is utilized for generating a stable quiescent current to provide the push-pull output stage a stable quiescent bias voltage. In this case, the operational amplifier 20 not only has a rail-to-rail common-mode input and output range, but also has a folded cascade structure capable of generating high gain, a class AB output stage and least quiescent paths. However, the use of the floating current source IS increases the number of the transistors significantly, and thus wiring of the operational amplifier 20 becomes more complicated, so as to further increase the layout area and the difficulty for integrating circuits.